Pulse shortening circuit



May 23, 1950 PULSE WITHOUT DELAY DELAYED PULSE OUTPUT F/G-Z IN VEN TOR.

GORDON D FORBES Patented May 23, 1950 UNITED STATES PATENT 11 Claims.

The invention described'herein may be manufactured and used by or for the Government for governmental purposes, without the payment to me of any royalty thereon.

This invention relates to a pulse shortening circuit .and provides means for operating on a pulse havin a predetermined duration to obtain one or more pulses having substantially less duration. The invention in general contemplates the use of a pulse transformer wherein the original pulse tobe operatedupon isfed into the primary. The transformer 'hasfltwo'secondary circuits with different delays in each circuit. The two resulting pulses may be combined in a subtractive manner to obtain a resultant output.

Referring .tothe drawing, Figure 1 is acircuit diagram illustrating the invention Figure 2 is a chart showingthevoltage pulses.

A pulse transformer .LD has aprimary U having terminals l2 and [3 into which a pulse may be fed. The transformer has two secondaries I l and I5 which are preferably similar and are connected to a grounded common terminal It. Seeondary winding I5 has its outer terminal I! connected to a delay line I8. Delay line I8 may be of any type and in its simplest form may consist of an inductance.

Secondary winding M has its outer terminal l9 connected to a resistance 20, and the circuit continues on to junction 2| joining the delay line circuit. Both secondary windings are connected in opposition to each other with a pair of series connected impedances forming part of the circuit. It is preferred to have the value of resistance 20 equal to the resistance of delay line l8. With windings l4 and I5 equal, the attenuation suifered by the pulses in the two secondary windings will be equal. The circuit is preferably terminated by a resistance 22 connected between ground and output 23 with the value of resistance 22 being substantially equal to the characteristic impedance of delay line It. It is understood that 22 may be an impedance rather than a resistance. However, it is preferred to match the impedance to the pulse system so that reflections will be avoided.

Assuming that a negative pulse is impressed upon primary I2, positive and negative pulses will be induced in windings l4 and I5. Delay line l8 will cause a time displacement of the pulse induced in winding I5 relative to the pulse induced in winding M as seen when the pulses are combined at junction Zl. Since the resistances of i8 and 2t] are equal, the amplitude of the pulses will be equal. By adjusting or controlling the amount of delay, any desired displacement of one induced pulse with respect-to the o t her induced pulse may be obtained.

The output as shown in Figure 2 will consist of positive and negative pulses and may be utilized in any manner desired. Thus one of these pulses m be l mi ed in he usual ma ne by the use of a diode or similarmeans.

Wh isc a m d s:

1- A pu o teni circuit compri a pulse transformer having a primary receiving p e a pair or se o a y win n s hav n .a

grounded common-terminal and two outer terminals, said secondary winding b insconnee e in v riesli e re atiq m e fcrponne ne t uter te mina s o i s o dar w n ings t eh et e s i mea ncludi a p i o imredan es avine e n r ta at ect on nsiueed ul e an an qutp tc r t onnec d between th Juncti n o n ibetweensa d two in.-

pedances and ground, said output circuit having an impedance equal to a characteristic impedance of the pulse shortening system for matching the impedance of said pulse shortening system.

2. The system as defined in claim 1 wherein said secondary windings have substantially equal impedances and said series impedances have substantially equal resistances.

3. A pulse-shortening circuit comprising a pulse transformer having primary and secondary windings, said primary being connected to a source of pulses, a delay line and a substantially pure resistor forming a closed series circuit with said secondary winding, and an output circuit connected between the center of said secondary winding and the junction point between said line and said resistance.

4. A pulse-shortening circuit as defined in claim 3 in which the resistance of said delay line is substantially equal to the ohmic resistance of said resistor.

5. A pulse-shortening circuit as defined in claim 3 in which the impedance of the output circuit matches the impedance connected across said output circuit on the input side of said output circuit, and in which the resistance component of said line is equal to the resistance of said resistor.

6. A pulse-shortening circuit comprising a pulse transformer having a primary and a secondary winding, said primary winding being connected to a source of pulses, a center tap on said secondary winding, said tap being connected to ground, said center tap dividing said secondary winding into two electrically equal parts, serially connected inductance and resistor connected across said secondary winding, the resistance of said inductance being equal to the resistance of said resistor, and an output circuit connected between the junction of said inductance and re-" sistance on one side and ground on the other side, the reactive and resistive components of the impedance of said coil being adjusted to produce positive and negative pulses in said output circuit as the result of two currents of opposite polarities impressed on said output circuit by said two parts of said secondary winding.

'7. A pulse shortening circuit comprising a pulse transformer having a primary, receiving pulses, a secondary having an intermediate terminal and two outer terminals to provide oppositely phased potentials with respect to said intermedi', ate terminal, a pair of impedances having a difference in retardation effect on said pulses connected in a closed series circuit between said outer terminals, the amount of said difference being less than the duration of said pulses, and

an output circuit connected between said intermediateterminal and the junction between said pair of impedances, said output circuit having 'an impedance equal to a characteristic impeda closed series circuit with said secondary winding, and an output circuit connected between an intermediate point on said secondary winding and the junction point of said impedances.

10. A pulse-transforming circuit comprising a pulse transformer having primary and secondary windings, said primarybeing connected to a source of pulses, a delay line and a substantially pure resistor forming a closed series circuit with amount of said difference being less than the duration of said pulses, and means coupled to both circuit means to derive an output having an instantaneous amplitude equal to the algebraic sum of the instantaneous amplitudes of the pulse components in said pair of circuit means.

GORDON DONALD FORBES.

REFERENCES CITED The following'references areof record in the file of this patent:

UNITED STATES PATENTS Date Number Name 2,190,504 Schlesinger Feb.'13, 1940 2,226,459 Bingley Dec. 24, 1940 2,252,442 Schlesinger Aug. 12, 1941 2,287,174 Heising June 23, 1942 

